The present invention relates to a semiconductor device and a method of manufacturing the same and, more particularly, to a connection structure for a charge protective layer for an electrode on a gate insulating film and an upper wiring layer, and a method of manufacturing the same.
Current semiconductor memory devices are roughly classified into volatile memories represented by a DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory), and nonvolatile memories represented by a flash EEPROM (Electrically Erasable and Programmable Read Only Memory).
As a semiconductor element constituting the former, a CMOS (Complementary Metal-Oxide Semiconductor) transistor is mainly used. As a semiconductor element constituting the latter, a floating gate type transistor is used. In the floating gate type transistor, source and drain regions are formed on the semiconductor surface, and a channel region is formed between the source and drain regions. The first gate insulating film, a floating gate electrode, the second gate insulating film, and a control gate electrode are sequentially formed on the channel region to constitute the so-called floating gate type transistor.
In the manufacture of such a floating gate type transistor, the first-layer gate electrode serving as the floating gate electrode is formed on a silicon oxide film on the major surface of the semiconductor substrate, an insulating interlayer film as a composite film of the silicon oxide film and a silicon nitride film is formed on the first-layer gate electrode, and the second-layer gate electrode serving as the control gate electrode is formed on the insulating interlayer film.
In this structure, nonvolatile storage information charges are accumulated in the floating gate electrode serving as the first-layer gate electrode. The information charges are written and erased by injecting electrons from the semiconductor substrate into the floating gate electrode and discharging electrons from the floating gate electrode to the semiconductor substrate, respectively.
In the manufacturing process of a flash memory constituted by a floating gate type transistor, the floating gate type transistor is exposed to a plasma atmosphere depending on the process. For example, in the dry etching process of a wiring layer, the insulating interlayer film where the wiring layer is formed or the word lines of the flash memory are charged in the plasma atmosphere. The word lines are formed by connecting a predetermined number of control gate electrodes of the floating gate type transistors constituting the nonvolatile memory elements of the memory cell portion.
When the word line is negatively charged, a large amount of holes are injected from the semiconductor substrate into the floating gate electrode. This causes dielectric breakdown of the first gate insulating film under the floating gate electrode. Alternatively, the floating gate electrode is positively charged to vary the threshold of the memory cell, and accordingly the threshold distribution of the flash memories after the manufacturing process widens largely. In this case, when shipping the flash memories, the threshold voltages must be uniformed in the inspecting process.
In order to solve these problems, conventionally, a charge prevention protective diode element is connected to the word line. This technique is described in, e.g., Japanese Patent Laid-Open No. 7-244991. A structure in which an electrode on a gate insulating film is connected to a diffusion layer, i.e., a protective diode, in this manner is similarly found in a semiconductor device constituted by a MOS transistor.
The technique described in the precedent reference described above will be described as the prior art with reference to FIGS. 5A and 5B. FIG. 5A shows a flash memory in which an insulating interlayer film shown in FIG. 5B is omitted. Referring to FIG. 5A, a source/drain diffusion layer 102 is formed on a silicon substrate 101. A floating gate electrode 103 is formed, and furthermore a word line 104, i.e., a control gate electrode, is formed. In this manner, a plurality of memory cells constituted by floating gate type transistors are formed in the memory cell array portion.
The word line 104 disposed in the memory cell array portion is electrically connected to a first aluminum wiring layer 106 through a contact hole 105. The first aluminum wiring layer 106 is electrically connected to a protective diffusion layer 108 through a contact hole 107. The diffusion junction of the protective diffusion layer 108 and silicon substrate 101 constitutes the protective diode element described above. The first aluminum wiring layer 106 is connected to a second aluminum wiring layer 110 through a through hole 109. The second aluminum wiring layer 110 is connected to a peripheral circuit portion.
In this manner, the word lines disposed in the memory cell array portion are respectively connected to the protective diode elements and to the peripheral circuit portion.
The sectional structure of this region will be described with reference to FIG. 5B. Referring to FIG. 5B, a field oxide film 111 is selectively formed on the surface of the silicon substrate 101 having a p-type conductivity. The floating gate electrode 103 is formed on the silicon substrate 101 through a gate insulating film 112. The word line 104 is formed to cover a gate insulating film 113 formed on the surface of the floating gate electrode 103. Furthermore, the protective diffusion layer 108 having an n-type conductivity is formed at a predetermined region on the surface of the silicon substrate 101. This p-n junction constitutes the protective diode element described above.
An insulating interlayer film 114 covering the entire surface of the structure is formed, and the contact hole 105 reaching the word line 104 and the contact hole 107 reaching the protective diffusion layer 108 are formed in the insulating interlayer film 114. The contact holes 105 and 107 are filled with metal plugs 115 and 116, respectively. The metal plugs 115 and 116 are connected to the first aluminum wiring layer 106 formed on the insulating interlayer film 114.
An insulating interlayer film 117 covering the first aluminum wiring layer 106 is formed, and the through hole 109 reaching the first aluminum wiring layer 106 is formed in the insulating interlayer film 117. The second aluminum wiring layer 110 is connected to the first aluminum wiring layer 106 through the through hole 109.
In the prior art described above, the following two major problems arise. The first problem is that, when the protective diode element for charge prevention of the control gate electrode, i.e., of the word line 104, is formed, the area of the protective diffusion layer 108 described above increases. If the protective diffusion layers 108 are formed in units of word lines 104, the area of the resultant semiconductor chip undesirably increases.
Usually, as the size of the contact holes 105 and 107 decreases, the contact holes 105 and 107 must indispensably be filled with the metal plugs 115 and 116. The metal plugs 115 and 116 are formed through deposition and dry etching, i.e., etch back, of a refractory metal. The second problem is that, in this etch back process, the word line 104 is charged with plasma ions or electrons of the dry etching gas to cause dielectric breakdown.
In general, at a certain stage of the manufacturing process of a semiconductor device or a MOS transistor, the gate electrode of the MOS transistor, e.g., the word line of the semiconductor device, is insulated by an insulating film, e.g., a field oxide film, a gate insulating film, or an insulating interlayer film, and is set in a floating state. This eliminates the discharge path for the charges accumulated when the gate electrode is exposed to the plasma as described above and charged. Such plasma charging of the word line or the like causes dielectric breakdown of the gate insulating film, leading to a decrease in the manufacturing yield of the semiconductor device.